DIMM

A DIMM or bifold in-line anamnesis module, comprises a alternation of activating random-access anamnesis chip circuits. These modules are army on a printed ambit lath and advised for use in claimed computers, workstations and servers. DIMMs began to alter SIMMs (single in-line anamnesis modules) as the absolute blazon of anamnesis bore as Intel P5-based Pentium processors began to accretion bazaar share.

The capital aberration amid SIMMs and DIMMs is that DIMMs accept abstracted electrical contacts on anniversary ancillary of the module, while the contacts on SIMMs on both abandon are redundant. Another aberration is that accepted SIMMs accept a 32-bit abstracts path, while accepted DIMMs accept a 64-bit abstracts path. Since Intel's Pentium has (as do several added processors) a 64-bit bus width, it requires SIMMs installed in akin pairs in adjustment to complete the abstracts bus. The processor would again admission the two SIMMs simultaneously. DIMMs were alien to annihilate this practice.

The a lot of accepted types of DIMMs are:

72-pin SO-DIMM (not the aforementioned as a 72-pin SIMM), acclimated for FPM DRAM and EDO DRAM

100-pin DIMM, acclimated for printer SDRAM

144-pin SO-DIMM, acclimated for SDR SDRAM

168-pin DIMM, acclimated for SDR SDRAM (less frequently for FPM/EDO DRAM in workstations/servers)

172-pin MicroDIMM, acclimated for DDR SDRAM

184-pin DIMM, acclimated for DDR SDRAM

200-pin SO-DIMM, acclimated for DDR SDRAM and DDR2 SDRAM

204-pin SO-DIMM, acclimated for DDR3 SDRAM

214-pin MicroDIMM, acclimated for DDR2 SDRAM

240-pin DIMM, acclimated for DDR2 SDRAM, DDR3 SDRAM and FB-DIMM DRAM

244-pin MiniDIMM, acclimated for DDR2 SDRAM

168-pin SDRAM

On the basal bend of 168-pin DIMMs there are 2 notches, and the area of anniversary cleft determines a accurate affection of the module.

The aboriginal cleft is DRAM key position. It represents RFU (reserved approaching use), registered, and unbuffered (in that adjustment from larboard to average to appropriate position).

The additional cleft is voltage key position. It represents 5.0V, 3.3V, and Aloof (order as above).

The high DIMM in the (topmost) photo is an unbuffered 3.3V 168-pin DIMM. DIMM slots abutment aswell DDR1, 2, 3 RAM.

DDR DIMMs

DDR, DDR2 and DDR3 all accept a altered pin-counts, and altered cleft positions

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SPD EPROM

A DIMM's accommodation and timing ambit may be articular with consecutive attendance ascertain (SPD), an added dent which contains advice about the bore blazon and timing for the anamnesis ambassador to be configured correctly.

Error correction

ECC DIMMs are those that accept added abstracts $.25 which can be acclimated by the arrangement anamnesis ambassador to ascertain and actual errors. There are abundant ECC schemes, but conceivably the a lot of accepted is Single Error Correct, Double Error Ascertain (SECDED) which uses an added byte per 64-bit word. ECC modules usually backpack a assorted of 9 instead of a assorted of 8 chips.

Ranking

Sometimes anamnesis modules are advised with two or added absolute sets of DRAM chips affiliated to the aforementioned abode and abstracts buses; anniversary such set is alleged a rank. Since all ranks allotment the aforementioned buses, alone one rank may be accessed at any accustomed time; it is defined by activating the agnate rank's dent baddest (CS) signal. All added ranks are deactivated for the continuance of the operation by accepting their agnate CS signals deactivated. DIMMs are currently getting frequently bogus with up to four ranks per module. Consumer DIMM vendors accept afresh amorphous to analyze amid individual and bifold ranked DIMMs.

DIMMs are generally referred to as "single-sided" or "double-sided" to call whether the DRAM chips are amid on one or both abandon of the module's printed ambit lath (PCB). However, these agreement may could cause confusion, as the concrete blueprint of the chips does not necessarily chronicle to how they are logically organized or accessed.

JEDEC absitively that the agreement "dual-sided," "double-sided," or "dual-banked" were not actual if activated to registered DIMMs.

Organization

Most DIMMs are congenital application "×4" (by 4) anamnesis chips or "×8" (by 8) anamnesis chips with 9 chips per side. "×4" or "×8" accredit to the abstracts amplitude of the DRAM chips in bits.

In the case of the "×4"-registered DIMMs, the abstracts amplitude per ancillary is 36 bits; therefore, the anamnesis ambassador (which requires 72 bits) needs to abode both abandon at the aforementioned time to apprehend or address the abstracts it needs. In this case, the alternate bore is single-ranked.

For "×8"-registered DIMMs, anniversary ancillary is 72 $.25 wide, so the anamnesis ambassador alone addresses one ancillary at a time (the alternate bore is dual-ranked).

Speeds

For assorted technologies, there are assertive bus and accessory alarm frequencies that are standardized. There is aswell a absitively classification for anniversary of these speeds for anniversary type.

SDR SDRAM DIMMs - These aboriginal ancillary registered DRAM DIMMs had the aforementioned bus abundance for data, abode and ascendancy lines.

PC66 = 66 MHz

PC100 = 100 MHz

PC133 = 133 MHz

DDR SDRAM (DDR1) DIMMs - DIMMs based on Bifold Abstracts Amount (DDR) DRAM accept abstracts but not the strobe at bifold the amount of the clock. This is accomplished by clocking on both the ascent and falling bend of the abstracts strobes.

PC1600 = 200 MHz abstracts & strobe / 100 MHz alarm for abode and control

PC2100 = 266 MHz abstracts & strobe / 133 MHz alarm for abode and control

PC2700 = 333 MHz abstracts & strobe / 166 MHz alarm for abode and control

PC3200 = 400 MHz abstracts & strobe / 200 MHz alarm for abode and control

DDR2 SDRAM DIMMs - DIMMs based on Bifold Abstracts Amount 2 (DDR2) DRAM aswell accept abstracts and abstracts strobe frequencies at bifold the amount of the clock. This is accomplished by clocking on both the ascent and falling bend of the abstracts strobes. The ability burning and voltage of DDR2 is decidedly lower than DDR(1) at the aforementioned speed.

PC2-3200 = 400 MHz abstracts & strobe / 200 MHz alarm for abode and control

PC2-4200 = 533 MHz abstracts & strobe / 266 MHz alarm for abode and control

PC2-5300 = 667 MHz abstracts & strobe / 333 MHz alarm for abode and control

PC2-6400 = 800 MHz abstracts & strobe / 400 MHz alarm for abode and control

PC2-8500 = 1066 MHz abstracts & strobe / 533 MHz alarm for abode and control

DDR3 SDRAM DIMMs - DIMMs based on Bifold Abstracts Amount 3(DDR3) DRAM accept abstracts and strobe frequencies at bifold the amount of the clock. This is accomplished by clocking on both the ascent and falling bend of the abstracts strobes. The ability burning and voltage of DDR3 is lower than DDR2 of the aforementioned speed.

PC3-6400 = 800 MHz abstracts & strobe / 400 MHz alarm for abode and control

PC3-8500 = 1066 MHz abstracts & strobe / 533 MHz alarm for abode and control

PC3-10600 = 1333 MHz abstracts & strobe / 667 MHz alarm for abode and control

PC3-12800 = 1600 MHz abstracts & strobe / 800 MHz alarm for abode and control

PC3-14900 = 1866 MHz abstracts & strobe / 933 MHz alarm for abode and control

PC3-17000 = 2133 MHz abstracts & strobe / 1066 MHz alarm for abode and control

Form factors

Several anatomy factors are frequently acclimated in DIMMs. Single Data Rate (SDR) SDRAM DIMMs frequently came in two capital heights: 1.7-inch and 1.5-inch. When 1U rackmount servers started acceptable popular, these anatomy agency Registered DIMMs had to bung into angled DIMM sockets to fit in the 1.75" top box. To allay this issue, the next standards of DDR DIMMs were created with a "Low Profile" (LP) acme of ~1.2". These fit into vertical DIMM sockets for a 1U platform. With the appearance of brand servers, the LP anatomy agency DIMMs accept already afresh been generally angled to fit in these space-constrained boxes. This led to the development of the Very Low Profile (VLP) anatomy agency DIMM with a acme of ~.72" (18.3 mm). The DDR3 JEDEC accepted for VLP DIMM acme is 18.75mm. These will fit angular in ATCA systems. Other DIMM anatomy factors cover the SO-DIMM, the Mini-DIMM and the VLP Mini-DIMM.