DDR, DDR2 and DDR3 all accept a altered pin-counts, and altered cleft positions
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SPD EPROM
A DIMM's accommodation and timing ambit may be articular with consecutive attendance ascertain (SPD), an added dent which contains advice about the bore blazon and timing for the anamnesis ambassador to be configured correctly.
Error correction
ECC DIMMs are those that accept added abstracts $.25 which can be acclimated by the arrangement anamnesis ambassador to ascertain and actual errors. There are abundant ECC schemes, but conceivably the a lot of accepted is Single Error Correct, Double Error Ascertain (SECDED) which uses an added byte per 64-bit word. ECC modules usually backpack a assorted of 9 instead of a assorted of 8 chips.
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SPD EPROM
A DIMM's accommodation and timing ambit may be articular with consecutive attendance ascertain (SPD), an added dent which contains advice about the bore blazon and timing for the anamnesis ambassador to be configured correctly.
Error correction
ECC DIMMs are those that accept added abstracts $.25 which can be acclimated by the arrangement anamnesis ambassador to ascertain and actual errors. There are abundant ECC schemes, but conceivably the a lot of accepted is Single Error Correct, Double Error Ascertain (SECDED) which uses an added byte per 64-bit word. ECC modules usually backpack a assorted of 9 instead of a assorted of 8 chips.
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